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Abstract: This paper presents a high-performance unrolled and pipelined architecture for efficient encoding and decoding of Polar Codes, targeting next-generation high-throughput and low-latency communication systems. The proposed design exploits full loop unrolling and deep pipelining techniques to maximize parallelism, thereby significantly increasing data throughput while maintaining reliable error-correction performance. By mapping the Polar Code factor graph directly onto dedicated hardware processing elements, the architecture minimizes control overhead and reduces critical path delay. Both encoder and decoder modules are optimized to support scalable code lengths and rates, enabling flexible integration in modern wireless standards such as 5G and beyond. Experimental analysis demonstrates that the proposed architecture achieves superior throughput and energy efficiency compared to conventional folded and semi-parallel designs, making it well suited for real-time, high-speed digital communication applications.